VALint: the NEEDS Verilog-A Checker (BETA)

By Xufeng Wang¹; Geoffrey Coram²; Colin McAndrew³

1. Purdue University 2. Analog Devices, Inc. 3. Freescale Semiconductor

Verilog-A lint and pretty printer created by NEEDS

Launch Tool

You must login before you can run this tool.

Version 1.0.0 - published on 31 Mar 2017

doi:10.4231/D3HX15S0V cite this

Open source: license | download

View All Supporting Documents

• About
• Usage
• Citations
• Questions
• Reviews
• Wishlist
• Versions

Recent Questions

Ask a question

Recent Questions (1-3 of 3)

1691	Difference between “parameter real” and “real” Asked by Saurabh Vinayak Suryavanshi @ 7:28 pm on 01 Mar 2016 • Open • 1		0 Like
1654	segmentation fault? Asked by Geoffrey Coram @ 3:01 pm on 07 Jan 2016 • Open • 1		0 Like
1653	issue with Makefile Asked by Geoffrey Coram @ 3:59 pm on 06 Jan 2016 • Open • 0		0 Like